The invention relates to a substrate having a depression suitable for an integrated circuit configuration and to a method for its fabrication.
In K. Yamada et al. xe2x80x9cA deep-trenched capacity technology for 4 megabit dynamic RAMxe2x80x9d, IEDM (1985) 702, a capacitor disposed in a depression in a substrate is described. In the depression, a capacitor dielectric is produced on surfaces that have no edges. A photolithographic process initially produces the depression with a square cross section. In order to round off the edges, a thermal oxide about fifty nanometers (50 nm) thick is grown and then removed. The capacitor dielectric is then grown by thermal oxidation. The rounding of the edges reduces leakage currents. This is because if a thermal oxide is grown onto a surface which has an edge, the oxide at the edge turns out to be particularly thin, so that leakage currents therefore occur in the region of the edge.
Commonly owned German patent 195 19 160 (which correspond to U.S. Pat. No. 5,817,552) describes a DRAM cell configuration. In this DRAM configuration, a storage capacitor is disposed underneath a transistor. A gate electrode of the transistor and a storage node of the capacitor are disposed in a depression having a square cross section. A surface on which the capacitor dielectric is disposed has edges.
EP 0 852 396 describes a DRAM cell configuration in which a depression in a silicon substrate is produced for one memory cell. First of all, insulating structures are produced in the substrate. Then, bit lines are produced on the substrate. Upper regions of the depressions are produced, silicon being etched selectively with respect to the insulating structures and the bit lines down to a first depth. Then, flanks of the depressions are provided with a layer of SiO2 and a layer of silicon nitride. By anisotropic etching down to a second depth, lower regions of the depressions are produced. The lower regions of the depressions are then broadened by isotropic etching, the layer of SiO2 and the layer of silicon nitride protecting the upper regions. In the lower region of the depression, a storage capacitor of the memory cell is produced. In the upper region of the memory cell, part of a word line is produced, acting as a gate electrode of a transistor belonging to the memory cell.
Kenney (U.S. Pat. No. 5,365,097), Ozaki (U.S. Pat. No. 5,216,266) and EP-A-0 333 426 disclose substrates in which depressions define an upper and a lower region. The upper region has a larger cross-sectional area than the lower region. These regions can contain storage capacitors and switching transistors of memory cells.
It is accordingly an object of the invention to provide a Substrate assembly having a depression suitable for an integrated circuit configuration and method for its fabrication that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that specifies a substrate having a depression, which is suitable for an integrated circuit configuration. The depression can be part of a transistor having a control characteristic like those commonly occurring in planar MOS transistors. And, the transistor can be part of a capacitor with a high breakdown voltage.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a substrate assembly having a depression that is suitable for an integrated circuit configuration. The substrate assembly includes a substrate having a main surface and a depression formed therein reaching into the substrate from the main surface. The depression has an upper region, an adjacent lower region with a vicinity near the upper region, a first cross section, a second cross section, and an indentation at a transition from the upper region to the lower region. The first cross section cuts through the upper region parallel to the main surface. The first cross section is substantially square and has at least one corner. The second cross section cuts through the lower region parallel to the main surface. The second cross section corresponds to the first cross section at least in the vicinity. The second cross section is smaller than the first cross section. The second cross section is substantially circular. The second cross section has at least one corner corresponding respectively to the at least one corner of the first cross section. The corners of the second cross section are rounded off.
With the objects of the invention in view, there is also provided a method of fabricating a substrate assembly. The method includes producing a depression in a substrate, starting from a main surface of the substrate. The next step is generating an upper region and an adjacent lower region in the depression. The next step is producing a substantially square first cross section through the upper region parallel to the main surface having at least one corner. The next step is producing a second cross section through the lower region parallel to the main surface and corresponding to the first cross section, at least immediately in a vicinity of the upper region, with each corner being rounded off to make the second cross section substantially smaller than the first cross section. The next step is providing an indentation in the depression at a transition from the upper region to the lower region.
The problem is solved by a substrate having a depression that is suitable for an integrated circuit configuration. In the configuration, the depression reaches into the substrate, starting from a main surface of the substrate. The depression has an upper region and an adjacent lower region. A cross section through the upper region parallel to the main surface has at least one corner. A cross section through the lower region parallel to the main surface corresponds to the cross section of the upper region. This correspondence is at least immediately in the vicinity of the upper region. A difference may be that each corner is rounded off in such a way that the cross section of the lower region is smaller than the cross section of the upper region and the depression has an indentation at the transition from the upper region to the lower region.
The problem is further solved by a method of fabricating a substrate having a depression, which is suitable for an integrated circuit configuration in which the depression is produced in the substrate, starting from a main surface of the substrate. The depression is produced with an upper region and an adjacent lower region. The upper region has a cross section through the upper region parallel to the main surface has at least one corner. The lower region has a cross section through the lower region parallel to the main surface corresponding to the cross section of the upper region, at least immediately in the vicinity of the upper region. A difference can be that each corner is rounded off in such a way that the cross section of the lower region is smaller than the cross section of the upper region and the depression has an indentation at the transition from the upper region to the lower region.
The substrate can include an integrated circuit configuration. In the integrated circuit configuration, a first side surface of the depression, which is located in the upper region, can be part of a first component of the circuit configuration. A second side surface of the depression located in the lower region can be part of a second component of the circuit configuration. Because the first component and the second component are disposed one underneath the other, the circuit configuration can have a high packing density.
Because the cross section of the upper region has at least one corner, the cross section can have a straight edge, and the first surface, which is associated with the edge, can be flat. In this case, the cross section will have at least two corners terminating the edge. The second surface is disposed under the first surface. In the cross section of the lower region, both corners are rounded off. Consequently, the second surface is curved.
The invention is based on the finding that the growth of an oxide layer produced by thermal oxidation on a surface of a substrate depends on the alignment of the surface in relation to the crystal structure of the substrate. If the surface is flat, the oxide layer grows with a homogenous thickness, because the flat surface has a defined alignment in relation to the crystal structure of the substrate, as opposed to a curved surface. If the oxide layer is a gate dielectric of a MOS transistor, the gate dielectric that is grown onto the curved surface does not have a homogeneous thickness. Therefore, different regions of the transistor have different threshold voltages. This leads to inhomogeneous turn-off behavior and, therefore, unfavorable control characteristics of the transistor. These characteristics have a lower below-threshold slope. Because the first surface is flat, the first component can be a vertical transistor, whose control characteristic, with regard to the turn-off behavior, corresponds to that of a conventional planar MOS transistor.
The second component can, for example, be a capacitor whose capacitor dielectric is disposed on the second surface.
The curved second surface enables the lower region of the depression not to have any edges. This occurs if all the corners in the cross section of the lower region are rounded. Not having edges is advantageous because the capacitor dielectric then likewise has no edges. Therefore, edge-induced thin points in the capacitor dielectric, and also field distortions that lead to a reduction in the breakdown voltage of the capacitor, are avoided. In addition, the capacitor dielectric can be produced more easily if no edges must be covered.
Moreover, dislocation defects, which can be produced at edges during a temperature cycle by high notch stresses on account of different expansion coefficients, can be avoided.
For other components, such as micromechanical sensors or actuators, it may also be advantageous to be disposed on a flat surface or on a curved surface or to comprise these. In the depression, for example, a conductive structure may be disposed. In such a configuration, the upper region of the depression acts as part of a component and in the lower region of the depression acts as a contact that leads to a surface of the substrate facing away from the main surface.
The invention is not just suitable for an integrated circuit configuration. It may also be advantageous, for example for mechanical reasons, for the depression to have a flat first surface and a curved second surface which are disposed one under the other. It is possible, for example, for a connecting structure that connects the substrate to another substrate to be disposed in the depression.
In accordance with another feature of the invention, an auxiliary spacer being produced in the depression after the production of the upper region by material being deposited and etched may produce a substrate. Isotropic etching of the auxiliary spacer rounds its edges, so that an exposed part of a base of the depression that adjoins the auxiliary spacer has no corners. The lower region is then produced by the substrate being etched selectively with respect to the auxiliary spacer. Under the auxiliary spacer, the surface of the depression that is substantially parallel to the main surface is produced.
When the edges of the auxiliary spacer are rounded off, parts of the upper region of the depression that are not located in the vicinity of the edges of the upper region can be exposed. The auxiliary spacer then breaks up into parts that are disposed in edges of the upper regions.
The scope of the invention includes the upper region having curved side surfaces in addition to the first surface.
In accordance with another feature of the invention, the auxiliary spacer is partially removed before the production of the lower region. By partially removing the auxiliary spacer, selected parts of the areas of the upper region and of the lower region merge into one another without a step, that is, without an indentation.
In order to increase the packing density, the first surface, which is bounded at the sides by edges of the depression, has a dimension parallel to the main surface that is no greater than the minimum structure size F that can be fabricated in the technology used.
In order to increase the packing density, the cross section of the upper region can be substantially square. The side length of the square is preferably F. The cross section of the lower region is substantially circular; a diameter is equal to or less than F. The lower region of the depression is, for example, cylindrical.
Such an upper region is difficult to produce by a simple masked photolithographic etching process. This is difficult because a lack of sharpness in the photolithography leads to rounding of edges at these small dimensions. The result is that the first surface is curved. The scope of the invention includes producing the upper region by two trenches being produced first with the aid of a strip-like first mask. A distance between the trenches is preferably F. Then, the trenches are filled with structures. To this end, for example, SiO2 can be deposited and etched back. After the production of the structures, the substrate is etched selectively with respect to the structures with the aid of a strip-like second mask. The second mask has at least two strips running transversely with respect to the trenches and having a distance from each other that is preferably F. In this way, the upper region of the depression, which has edges, is produced between the trenches and between the strips. The upper region also can be produced by a different process in such a way that its cross section is square with a side length of F.
In accordance with another feature of the invention, the distance between the trenches and the distance between the strips of the second mask is greater than F, and therefore the cross section of the upper region being greater than F2.
The substrate can include a DRAM cell configuration. The depression is part of a memory cell that includes a vertical transistor and a storage capacitor connected in series with it. The lower region of the depression is provided with a capacitor dielectric. A storage node of the storage capacitor is for the most part disposed in the lower region. The upper region of the depression is provided with a gate dielectric. A gate electrode of the transistor is placed in the upper region on at least the first surface. A lower source/drain region of the transistor is disposed in the substrate and connected electrically to the storage node. An upper source/drain region of the transistor is connected to a bit line. The gate electrode is connected to a word line. The word line and the bit line are preferably located above the main surface, so that they can be produced from materials with a high electrical conductivity and can be structured together with gate electrodes of transistors of a periphery of the cell configuration.
In accordance with another feature of the invention, the substrate can be a semiconductor substrate. The semiconductor substrate can be, for example, silicon or germanium.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a substrate having a depression, which is suitable for an integrated circuit configuration, and method for its fabrication, it is nevertheless not intended to be limited to the details shown, because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.